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Resetting two CD4017 counters simultaneously, only one resets
How to use Counters ONLY to construct a School Bell circuit?Using a diode to ensure current flows in only one direction, without causing a voltage dropHaving an issue of implementing an 8 bit counter from two 4 bit countersHaving an issue connecting two 4-bit Synchronous Up Down countersWiring two LDOs in parallel with only one diode betweenCan this circuit validate AT89Cx051 micro if best valued components are used?Deriving two independently stoppable clocks from one clockResetting CD4017 Counter when power source is OFFProblem with adding two counters in series on an FPGATwo source one output
$begingroup$
I am working on a simple 24-hour clock based on the CD4017. To reset when the clock reaches the 24th hour, two diodes are used to produce an "and" logic when the 2 digit and 4 digit LEDs receive a high output from the CD4017. The output from these diodes are connected to the reset pins of both CD4017 chips.
What I have found happens in practice is that the U-H10 chip resets as expected, but the U-H01 chip does not. I imagine this could be due to a delay in the signal due to differences in trace lengths (maybe 10-20mm) and or placements somehow creating a tiny RC effect. (One has more vias than the other.) I tried adding a small cap, shorting resistors R138 and R6, as well as removing R18 (on an etched PCB, not a breadboard.) I also checked the reset (pin 15) of U-H01 and it does not APPEAR to be shorted to ground.
Has anyone else faced a similar problem? Ideas?
diodes clock counter reset cd4017
asked 2 hours ago
HarritoHarrito
162
New contributor
Harrito is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
add a comment |
$begingroup$
I am working on a simple 24-hour clock based on the CD4017. To reset when the clock reaches the 24th hour, two diodes are used to produce an "and" logic when the 2 digit and 4 digit LEDs receive a high output from the CD4017. The output from these diodes are connected to the reset pins of both CD4017 chips.
What I have found happens in practice is that the U-H10 chip resets as expected, but the U-H01 chip does not. I imagine this could be due to a delay in the signal due to differences in trace lengths (maybe 10-20mm) and or placements somehow creating a tiny RC effect. (One has more vias than the other.) I tried adding a small cap, shorting resistors R138 and R6, as well as removing R18 (on an etched PCB, not a breadboard.) I also checked the reset (pin 15) of U-H01 and it does not APPEAR to be shorted to ground.
Has anyone else faced a similar problem? Ideas?
diodes clock counter reset cd4017
asked 2 hours ago
HarritoHarrito
162
New contributor
Harrito is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
add a comment |
$begingroup$
I am working on a simple 24-hour clock based on the CD4017. To reset when the clock reaches the 24th hour, two diodes are used to produce an "and" logic when the 2 digit and 4 digit LEDs receive a high output from the CD4017. The output from these diodes are connected to the reset pins of both CD4017 chips.
What I have found happens in practice is that the U-H10 chip resets as expected, but the U-H01 chip does not. I imagine this could be due to a delay in the signal due to differences in trace lengths (maybe 10-20mm) and or placements somehow creating a tiny RC effect. (One has more vias than the other.) I tried adding a small cap, shorting resistors R138 and R6, as well as removing R18 (on an etched PCB, not a breadboard.) I also checked the reset (pin 15) of U-H01 and it does not APPEAR to be shorted to ground.
Has anyone else faced a similar problem? Ideas?
diodes clock counter reset cd4017
asked 2 hours ago
HarritoHarrito
162
New contributor
Harrito is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
$endgroup$
I am working on a simple 24-hour clock based on the CD4017. To reset when the clock reaches the 24th hour, two diodes are used to produce an "and" logic when the 2 digit and 4 digit LEDs receive a high output from the CD4017. The output from these diodes are connected to the reset pins of both CD4017 chips.
What I have found happens in practice is that the U-H10 chip resets as expected, but the U-H01 chip does not. I imagine this could be due to a delay in the signal due to differences in trace lengths (maybe 10-20mm) and or placements somehow creating a tiny RC effect. (One has more vias than the other.) I tried adding a small cap, shorting resistors R138 and R6, as well as removing R18 (on an etched PCB, not a breadboard.) I also checked the reset (pin 15) of U-H01 and it does not APPEAR to be shorted to ground.
Has anyone else faced a similar problem? Ideas?
diodes clock counter reset cd4017
diodes clock counter reset cd4017
asked 2 hours ago
HarritoHarrito
162
New contributor
Harrito is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 2 hours ago
HarritoHarrito
162
New contributor
Harrito is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 2 hours ago
HarritoHarrito
162
New contributor
Harrito is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 2 hours ago
HarritoHarrito
162
asked 2 hours ago
HarritoHarrito
162
162
New contributor
Harrito is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
New contributor
Harrito is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
Harrito is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
add a comment |
add a comment |
2 Answers
2
active
oldest
votes
$begingroup$
You're using a "glitch" to reset your counters. In other words, when the reset pulse starts, it immediately removes the conditions for its own creation, so it's only as wide as the propagation delay through one of the counters.
Clearly, one of those counters is faster than the other, so it resets successfully, while the other does not. This is why this is considered poor design practice, and why synchronous counting was invented — it only works under certain conditions.
The fix is to use the glitch to trigger a monostable timer (e.g., half of a 4098) that will guarantee the minimum reset pulse width for both counters. The reset won't occur until the timer is successfully triggered, by which time, it doesn't matter if the glitch goes away.
I see that you have removed R18's connection to ground, but I don't see any other provision to pull that node high. If that node is just floating, then you're just getting capacitive coupling and/or leakage current through the diodes for your reset pulse, compounding the problem.
answered 1 hour ago
Dave Tweed♦Dave Tweed
122k9152264
$endgroup$
$begingroup$
thank you. You are right on many counts. For those unfamiliar with the CD4017, the reset is high, not low. From the TI datasheet "A high RESET signal clears the counter to its zero count." As you can imagine, R18 was removed for trouble shooting to ensure that traces were as designed and the circuit had been implemented as drawn (even if incorrect.) Due to my limited access to parts, I'll likely try using a 555 timer or a couple of 2N2222 transistors. I image this case is where a reset supervisor chip (ADM803) would come in handy.
$endgroup$
– Harrito
43 mins ago
add a comment |
$begingroup$
R18 should go to Vdd, not ground. Otherwise the RESET line will never go high (the diodes can only pull it low).
Edit: Depending on the logic family you are using, there may be enough diode and stray capacitance in the diodes to cause false resets. Assume HC logic you can shunt R18 with about 20pF. And make sure R18 connects to Vdd (+5V).
answered 1 hour ago
Spehro PefhanySpehro Pefhany
211k5162426
$endgroup$
1
$begingroup$
Obviously, if ONE of the counters is resetting, then something is working. We have to assume that the schematic is wrong in that detail. Note the rework on R18 (lower left corner) in the PCB photo.
$endgroup$
– Dave Tweed♦
1 hour ago
1
$begingroup$
Capacitive kick through the diodes?
$endgroup$
– Transistor
1 hour ago
$begingroup$
@Transistor Could be. Shunt R18 with ~20pF and make sure it's connected to Vdd. Don't add too much capacitance or other problems may crop up.
$endgroup$
– Spehro Pefhany
1 hour ago
$begingroup$
Even with the suggested capacitance, this is still not a reliable solution. Now you're counting on the fact that the two counters have exactly the same logic threshold on their reset inputs.
$endgroup$
– Dave Tweed♦
1 hour ago
$begingroup$
@DaveTweed Yes, it's probably not a great solution. Your suggestion of a one-shot is much better. If OP does try the above, they should also reduce the resistance of R18 to 2K or so (HC logic) to give the propogation delay a chance to make up for the any difference in logic thresholds (which would tend to reset the slower one only, and the problem is magnified by the slow rise time vs. fast fall time of the diode AND). We used to do ugly things with diodes and capacitors but a one-shot or at least a Schmitt trigger + RC is much more elegant.
$endgroup$
– Spehro Pefhany
1 hour ago
add a comment |
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2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
$begingroup$
You're using a "glitch" to reset your counters. In other words, when the reset pulse starts, it immediately removes the conditions for its own creation, so it's only as wide as the propagation delay through one of the counters.
Clearly, one of those counters is faster than the other, so it resets successfully, while the other does not. This is why this is considered poor design practice, and why synchronous counting was invented — it only works under certain conditions.
The fix is to use the glitch to trigger a monostable timer (e.g., half of a 4098) that will guarantee the minimum reset pulse width for both counters. The reset won't occur until the timer is successfully triggered, by which time, it doesn't matter if the glitch goes away.
I see that you have removed R18's connection to ground, but I don't see any other provision to pull that node high. If that node is just floating, then you're just getting capacitive coupling and/or leakage current through the diodes for your reset pulse, compounding the problem.
answered 1 hour ago
Dave Tweed♦Dave Tweed
122k9152264
$endgroup$
$begingroup$
thank you. You are right on many counts. For those unfamiliar with the CD4017, the reset is high, not low. From the TI datasheet "A high RESET signal clears the counter to its zero count." As you can imagine, R18 was removed for trouble shooting to ensure that traces were as designed and the circuit had been implemented as drawn (even if incorrect.) Due to my limited access to parts, I'll likely try using a 555 timer or a couple of 2N2222 transistors. I image this case is where a reset supervisor chip (ADM803) would come in handy.
$endgroup$
– Harrito
43 mins ago
add a comment |
$begingroup$
You're using a "glitch" to reset your counters. In other words, when the reset pulse starts, it immediately removes the conditions for its own creation, so it's only as wide as the propagation delay through one of the counters.
Clearly, one of those counters is faster than the other, so it resets successfully, while the other does not. This is why this is considered poor design practice, and why synchronous counting was invented — it only works under certain conditions.
The fix is to use the glitch to trigger a monostable timer (e.g., half of a 4098) that will guarantee the minimum reset pulse width for both counters. The reset won't occur until the timer is successfully triggered, by which time, it doesn't matter if the glitch goes away.
I see that you have removed R18's connection to ground, but I don't see any other provision to pull that node high. If that node is just floating, then you're just getting capacitive coupling and/or leakage current through the diodes for your reset pulse, compounding the problem.
answered 1 hour ago
Dave Tweed♦Dave Tweed
122k9152264
$endgroup$
$begingroup$
thank you. You are right on many counts. For those unfamiliar with the CD4017, the reset is high, not low. From the TI datasheet "A high RESET signal clears the counter to its zero count." As you can imagine, R18 was removed for trouble shooting to ensure that traces were as designed and the circuit had been implemented as drawn (even if incorrect.) Due to my limited access to parts, I'll likely try using a 555 timer or a couple of 2N2222 transistors. I image this case is where a reset supervisor chip (ADM803) would come in handy.
$endgroup$
– Harrito
43 mins ago
add a comment |
$begingroup$
You're using a "glitch" to reset your counters. In other words, when the reset pulse starts, it immediately removes the conditions for its own creation, so it's only as wide as the propagation delay through one of the counters.
Clearly, one of those counters is faster than the other, so it resets successfully, while the other does not. This is why this is considered poor design practice, and why synchronous counting was invented — it only works under certain conditions.
The fix is to use the glitch to trigger a monostable timer (e.g., half of a 4098) that will guarantee the minimum reset pulse width for both counters. The reset won't occur until the timer is successfully triggered, by which time, it doesn't matter if the glitch goes away.
I see that you have removed R18's connection to ground, but I don't see any other provision to pull that node high. If that node is just floating, then you're just getting capacitive coupling and/or leakage current through the diodes for your reset pulse, compounding the problem.
answered 1 hour ago
Dave Tweed♦Dave Tweed
122k9152264
$endgroup$
You're using a "glitch" to reset your counters. In other words, when the reset pulse starts, it immediately removes the conditions for its own creation, so it's only as wide as the propagation delay through one of the counters.
Clearly, one of those counters is faster than the other, so it resets successfully, while the other does not. This is why this is considered poor design practice, and why synchronous counting was invented — it only works under certain conditions.
The fix is to use the glitch to trigger a monostable timer (e.g., half of a 4098) that will guarantee the minimum reset pulse width for both counters. The reset won't occur until the timer is successfully triggered, by which time, it doesn't matter if the glitch goes away.
I see that you have removed R18's connection to ground, but I don't see any other provision to pull that node high. If that node is just floating, then you're just getting capacitive coupling and/or leakage current through the diodes for your reset pulse, compounding the problem.
answered 1 hour ago
Dave Tweed♦Dave Tweed
122k9152264
edited 1 hour ago
answered 1 hour ago
Dave Tweed♦Dave Tweed
122k9152264
answered 1 hour ago
Dave Tweed♦Dave Tweed
122k9152264
answered 1 hour ago
Dave Tweed♦Dave Tweed
122k9152264
122k9152264
$begingroup$
thank you. You are right on many counts. For those unfamiliar with the CD4017, the reset is high, not low. From the TI datasheet "A high RESET signal clears the counter to its zero count." As you can imagine, R18 was removed for trouble shooting to ensure that traces were as designed and the circuit had been implemented as drawn (even if incorrect.) Due to my limited access to parts, I'll likely try using a 555 timer or a couple of 2N2222 transistors. I image this case is where a reset supervisor chip (ADM803) would come in handy.
$endgroup$
– Harrito
43 mins ago
add a comment |
$begingroup$
thank you. You are right on many counts. For those unfamiliar with the CD4017, the reset is high, not low. From the TI datasheet "A high RESET signal clears the counter to its zero count." As you can imagine, R18 was removed for trouble shooting to ensure that traces were as designed and the circuit had been implemented as drawn (even if incorrect.) Due to my limited access to parts, I'll likely try using a 555 timer or a couple of 2N2222 transistors. I image this case is where a reset supervisor chip (ADM803) would come in handy.
$endgroup$
– Harrito
43 mins ago
$begingroup$
thank you. You are right on many counts. For those unfamiliar with the CD4017, the reset is high, not low. From the TI datasheet "A high RESET signal clears the counter to its zero count." As you can imagine, R18 was removed for trouble shooting to ensure that traces were as designed and the circuit had been implemented as drawn (even if incorrect.) Due to my limited access to parts, I'll likely try using a 555 timer or a couple of 2N2222 transistors. I image this case is where a reset supervisor chip (ADM803) would come in handy.
$endgroup$
– Harrito
43 mins ago
$begingroup$
thank you. You are right on many counts. For those unfamiliar with the CD4017, the reset is high, not low. From the TI datasheet "A high RESET signal clears the counter to its zero count." As you can imagine, R18 was removed for trouble shooting to ensure that traces were as designed and the circuit had been implemented as drawn (even if incorrect.) Due to my limited access to parts, I'll likely try using a 555 timer or a couple of 2N2222 transistors. I image this case is where a reset supervisor chip (ADM803) would come in handy.
$endgroup$
– Harrito
43 mins ago
add a comment |
$begingroup$
R18 should go to Vdd, not ground. Otherwise the RESET line will never go high (the diodes can only pull it low).
Edit: Depending on the logic family you are using, there may be enough diode and stray capacitance in the diodes to cause false resets. Assume HC logic you can shunt R18 with about 20pF. And make sure R18 connects to Vdd (+5V).
answered 1 hour ago
Spehro PefhanySpehro Pefhany
211k5162426
$endgroup$
1
$begingroup$
Obviously, if ONE of the counters is resetting, then something is working. We have to assume that the schematic is wrong in that detail. Note the rework on R18 (lower left corner) in the PCB photo.
$endgroup$
– Dave Tweed♦
1 hour ago
1
$begingroup$
Capacitive kick through the diodes?
$endgroup$
– Transistor
1 hour ago
$begingroup$
@Transistor Could be. Shunt R18 with ~20pF and make sure it's connected to Vdd. Don't add too much capacitance or other problems may crop up.
$endgroup$
– Spehro Pefhany
1 hour ago
$begingroup$
Even with the suggested capacitance, this is still not a reliable solution. Now you're counting on the fact that the two counters have exactly the same logic threshold on their reset inputs.
$endgroup$
– Dave Tweed♦
1 hour ago
$begingroup$
@DaveTweed Yes, it's probably not a great solution. Your suggestion of a one-shot is much better. If OP does try the above, they should also reduce the resistance of R18 to 2K or so (HC logic) to give the propogation delay a chance to make up for the any difference in logic thresholds (which would tend to reset the slower one only, and the problem is magnified by the slow rise time vs. fast fall time of the diode AND). We used to do ugly things with diodes and capacitors but a one-shot or at least a Schmitt trigger + RC is much more elegant.
$endgroup$
– Spehro Pefhany
1 hour ago
add a comment |
$begingroup$
R18 should go to Vdd, not ground. Otherwise the RESET line will never go high (the diodes can only pull it low).
Edit: Depending on the logic family you are using, there may be enough diode and stray capacitance in the diodes to cause false resets. Assume HC logic you can shunt R18 with about 20pF. And make sure R18 connects to Vdd (+5V).
answered 1 hour ago
Spehro PefhanySpehro Pefhany
211k5162426
$endgroup$
1
$begingroup$
Obviously, if ONE of the counters is resetting, then something is working. We have to assume that the schematic is wrong in that detail. Note the rework on R18 (lower left corner) in the PCB photo.
$endgroup$
– Dave Tweed♦
1 hour ago
1
$begingroup$
Capacitive kick through the diodes?
$endgroup$
– Transistor
1 hour ago
$begingroup$
@Transistor Could be. Shunt R18 with ~20pF and make sure it's connected to Vdd. Don't add too much capacitance or other problems may crop up.
$endgroup$
– Spehro Pefhany
1 hour ago
$begingroup$
Even with the suggested capacitance, this is still not a reliable solution. Now you're counting on the fact that the two counters have exactly the same logic threshold on their reset inputs.
$endgroup$
– Dave Tweed♦
1 hour ago
$begingroup$
@DaveTweed Yes, it's probably not a great solution. Your suggestion of a one-shot is much better. If OP does try the above, they should also reduce the resistance of R18 to 2K or so (HC logic) to give the propogation delay a chance to make up for the any difference in logic thresholds (which would tend to reset the slower one only, and the problem is magnified by the slow rise time vs. fast fall time of the diode AND). We used to do ugly things with diodes and capacitors but a one-shot or at least a Schmitt trigger + RC is much more elegant.
$endgroup$
– Spehro Pefhany
1 hour ago
add a comment |
$begingroup$
R18 should go to Vdd, not ground. Otherwise the RESET line will never go high (the diodes can only pull it low).
Edit: Depending on the logic family you are using, there may be enough diode and stray capacitance in the diodes to cause false resets. Assume HC logic you can shunt R18 with about 20pF. And make sure R18 connects to Vdd (+5V).
answered 1 hour ago
Spehro PefhanySpehro Pefhany
211k5162426
$endgroup$
R18 should go to Vdd, not ground. Otherwise the RESET line will never go high (the diodes can only pull it low).
Edit: Depending on the logic family you are using, there may be enough diode and stray capacitance in the diodes to cause false resets. Assume HC logic you can shunt R18 with about 20pF. And make sure R18 connects to Vdd (+5V).
answered 1 hour ago
Spehro PefhanySpehro Pefhany
211k5162426
edited 1 hour ago
answered 1 hour ago
Spehro PefhanySpehro Pefhany
211k5162426
answered 1 hour ago
Spehro PefhanySpehro Pefhany
211k5162426
answered 1 hour ago
Spehro PefhanySpehro Pefhany
211k5162426
211k5162426
1
$begingroup$
Obviously, if ONE of the counters is resetting, then something is working. We have to assume that the schematic is wrong in that detail. Note the rework on R18 (lower left corner) in the PCB photo.
$endgroup$
– Dave Tweed♦
1 hour ago
1
$begingroup$
Capacitive kick through the diodes?
$endgroup$
– Transistor
1 hour ago
$begingroup$
@Transistor Could be. Shunt R18 with ~20pF and make sure it's connected to Vdd. Don't add too much capacitance or other problems may crop up.
$endgroup$
– Spehro Pefhany
1 hour ago
$begingroup$
Even with the suggested capacitance, this is still not a reliable solution. Now you're counting on the fact that the two counters have exactly the same logic threshold on their reset inputs.
$endgroup$
– Dave Tweed♦
1 hour ago
$begingroup$
@DaveTweed Yes, it's probably not a great solution. Your suggestion of a one-shot is much better. If OP does try the above, they should also reduce the resistance of R18 to 2K or so (HC logic) to give the propogation delay a chance to make up for the any difference in logic thresholds (which would tend to reset the slower one only, and the problem is magnified by the slow rise time vs. fast fall time of the diode AND). We used to do ugly things with diodes and capacitors but a one-shot or at least a Schmitt trigger + RC is much more elegant.
$endgroup$
– Spehro Pefhany
1 hour ago
add a comment |
1
$begingroup$
Obviously, if ONE of the counters is resetting, then something is working. We have to assume that the schematic is wrong in that detail. Note the rework on R18 (lower left corner) in the PCB photo.
$endgroup$
– Dave Tweed♦
1 hour ago
1
$begingroup$
Capacitive kick through the diodes?
$endgroup$
– Transistor
1 hour ago
$begingroup$
@Transistor Could be. Shunt R18 with ~20pF and make sure it's connected to Vdd. Don't add too much capacitance or other problems may crop up.
$endgroup$
– Spehro Pefhany
1 hour ago
$begingroup$
Even with the suggested capacitance, this is still not a reliable solution. Now you're counting on the fact that the two counters have exactly the same logic threshold on their reset inputs.
$endgroup$
– Dave Tweed♦
1 hour ago
$begingroup$
@DaveTweed Yes, it's probably not a great solution. Your suggestion of a one-shot is much better. If OP does try the above, they should also reduce the resistance of R18 to 2K or so (HC logic) to give the propogation delay a chance to make up for the any difference in logic thresholds (which would tend to reset the slower one only, and the problem is magnified by the slow rise time vs. fast fall time of the diode AND). We used to do ugly things with diodes and capacitors but a one-shot or at least a Schmitt trigger + RC is much more elegant.
$endgroup$
– Spehro Pefhany
1 hour ago
1
1
$begingroup$
Obviously, if ONE of the counters is resetting, then something is working. We have to assume that the schematic is wrong in that detail. Note the rework on R18 (lower left corner) in the PCB photo.
$endgroup$
– Dave Tweed♦
1 hour ago
$begingroup$
Obviously, if ONE of the counters is resetting, then something is working. We have to assume that the schematic is wrong in that detail. Note the rework on R18 (lower left corner) in the PCB photo.
$endgroup$
– Dave Tweed♦
1 hour ago
1
1
$begingroup$
Capacitive kick through the diodes?
$endgroup$
– Transistor
1 hour ago
$begingroup$
Capacitive kick through the diodes?
$endgroup$
– Transistor
1 hour ago
$begingroup$
@Transistor Could be. Shunt R18 with ~20pF and make sure it's connected to Vdd. Don't add too much capacitance or other problems may crop up.
$endgroup$
– Spehro Pefhany
1 hour ago
$begingroup$
@Transistor Could be. Shunt R18 with ~20pF and make sure it's connected to Vdd. Don't add too much capacitance or other problems may crop up.
$endgroup$
– Spehro Pefhany
1 hour ago
$begingroup$
Even with the suggested capacitance, this is still not a reliable solution. Now you're counting on the fact that the two counters have exactly the same logic threshold on their reset inputs.
$endgroup$
– Dave Tweed♦
1 hour ago
$begingroup$
Even with the suggested capacitance, this is still not a reliable solution. Now you're counting on the fact that the two counters have exactly the same logic threshold on their reset inputs.
$endgroup$
– Dave Tweed♦
1 hour ago
$begingroup$
@DaveTweed Yes, it's probably not a great solution. Your suggestion of a one-shot is much better. If OP does try the above, they should also reduce the resistance of R18 to 2K or so (HC logic) to give the propogation delay a chance to make up for the any difference in logic thresholds (which would tend to reset the slower one only, and the problem is magnified by the slow rise time vs. fast fall time of the diode AND). We used to do ugly things with diodes and capacitors but a one-shot or at least a Schmitt trigger + RC is much more elegant.
$endgroup$
– Spehro Pefhany
1 hour ago
$begingroup$
@DaveTweed Yes, it's probably not a great solution. Your suggestion of a one-shot is much better. If OP does try the above, they should also reduce the resistance of R18 to 2K or so (HC logic) to give the propogation delay a chance to make up for the any difference in logic thresholds (which would tend to reset the slower one only, and the problem is magnified by the slow rise time vs. fast fall time of the diode AND). We used to do ugly things with diodes and capacitors but a one-shot or at least a Schmitt trigger + RC is much more elegant.
$endgroup$
– Spehro Pefhany
1 hour ago
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